In a typical microprocessor chip, designers often use a pipelined circuit to perform certain operations, such as floating point computations, for increasing the chip's frequency. A pipelined circuit conventionally includes multiple pipeline stage circuits for performing the computations. Conventional pipeline stage circuits are often modified to increase the performance of the chip. However, high-performance pipeline stage circuits often substantially dissipate power when performing calculations. Even when functioning in an idle or sleep mode, conventional pipeline stage circuits dissipate a significant amount of power through leakage paths.
With the ever increasing demand for power in microprocessor chips, it is imperative that the power efficiency of every circuit in a microprocessor chip. Accordingly, techniques have been developed for reducing power consumption in microprocessor chips, such as placing pipeline stage circuits in a sleep mode. Techniques utilizing a sleep mode, however, tend to suffer from step-load problems. These problems result from an inductive effect in a power delivery line for the pipeline stage circuits. When pipeline stage circuits are waking up after being in a sleep mode, the circuits usually draw a large amount of current in a short period of time to sustain high-speed operation. This results in a step-load effect.
In order to overcome the step-load effect, an on-chip decoupling capacitance is enlarged or a dummy cycle is introduced in the pipeline stage circuits to prevent an inductive spike. Enlarging the on-chip decoupling capacitance, however, has not proved feasible for a variant demand for power during chip operation. Also, executing a dummy cycle tends to waste a considerable amount of power.